Reuse Design and Test using Object-Oriented Hierarchical Models Libraries
Résumé
We introduce in this paper an object-oriented VHDL Design and Test library in which are saved all the descriptions and testbenches developed during the Design and Validation phases. The design of complex manufactured systems is a task requiring a lot of time to be achieved. One way to speed up this task is to develop methodologies for creating highly reusable components and assisting the reuse process in the design and test phases. A set of recent works has recently dealt with reusable concepts and libraries in the VHDL Design and Test area. The originality of our approach lies in the facts that it is based on a strong notion of genericity of use, and on notions like the inheritance and abstraction links between the stored descriptions. We describe how managing inheritance between stored models can improve their classification and their accuracy, and how the abstraction hierarchy allows to describe a same model at various detail levels.
Domaines
Modélisation et simulation
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