Cell Architecture for Nanoelectronic Design

F. Martorell (1) , A. Rubio (1)

1 High Performance IC Design Group, DEE

Several nanoelectronic devices have been already proved. However, no architecture which makes use of them provides a feasible opportunity to build medium/large systems. Nanoarchitecture proposals only solve a small part of the problems needed to achieve a real design. In this paper, we propose and analyze a cell architecture that overcomes most of those at the gate level. Using the cell structure we build 2 and 3-input NAND gates showing their error probabilities. Finally, we outline a method to further improve the structure's tolerance by taking advantage of interferences among nanodevices. Using this improvement we show that it is possible to reduce the output standard deviation by a factor larger than $\sqrt{2}$ and restitute the signal levels using nanodevices.

Mots clés: Nanoarchitectures; fault-tolerance; defect-tolerance; noise-tolerance; averaging cell

Domaines: Science des matériaux [cond-mat.mtrl-sci]

F. Martorell, A. Rubio. Cell Architecture for Nanoelectronic Design. ENS 2006, Dec 2006, Paris, France. pp.114-119. ⟨hal-00166774⟩