Behavioral Fault Simulation for VHDL Description using DEVS Formalism

Laurent Capocchi (1) , Fabrice Bernardi (2) , Paul-Antoine Bisgambiglia (2) , Dominique Federici (2)

1 TIC
2 SPE - Sciences pour l'environnement

One of the main problems is that today the tools for test generation are unable to quickly and easily create and simulate behavioral fault models directly from the VHDL descriptions. A way to solve this problem is to encapsulate these descriptions in easily simulable and evolutive models using DEVS formalism and to define a Behavioral Fault Simulator based on fast fault list propagation technique allowing the reduction of the number of VHDL simulation.

Mots clés: VHDL descriptions; DEVS formalism; modeling; simulation; fault

Domaines: Modélisation et simulation

Laurent Capocchi, Fabrice Bernardi, Paul-Antoine Bisgambiglia, Dominique Federici. Behavioral Fault Simulation for VHDL Description using DEVS Formalism. IEEE Pacific Rim Dependable Computing International Conference (PRDC), Aug 2004, Papeete, France. ⟨hal-00165465⟩