A DEVS-based Modeling Behavioral Fault Simulator for RT-Level Digital Circuits

Laurent Capocchi (1) , Fabrice Bernardi (2) , Dominique Federici (2) , Paul-Antoine Bisgambiglia (2)

1 TIC
2 SPE - Sciences pour l'environnement

The domain of fault simulation for digital circuits described at the RT-level is currently under heavy researches. The goal of these researches is to define a fast and efficient methodology for the validation of test patterns very early in the design flow. We propose in this article a new approach for the modeling and the simulation of behavioral faults for digital circuits described in the VHDL language, using a discrete event approach. This methodology, based on the DEVS formalism, is implemented in a working prototype, and experimental results show the correctness of our approach and the efficiency of our behavioral fault simulator called BFS-DEVS. The fault model used to validate our results is essentially based on the stuck-at fault model since a good simple stuck-at faults coverage rate implies a good real faults coverage rate.

Mots clés: DEVS; fault simulation; testability; modeling; simulation

Domaines: Modélisation et simulation

Laurent Capocchi, Fabrice Bernardi, Dominique Federici, Paul-Antoine Bisgambiglia. A DEVS-based Modeling Behavioral Fault Simulator for RT-Level Digital Circuits. SCS Summer Computer Simulation Conference (SCSC04), Jul 2004, San Jose, United States. pp.481-486. ⟨hal-00165460⟩