Application of a design space exploration tool to enhance interleaver generation

Cyrille Chavet (1) , Philippe Coussy (1) , Pascal Urard (2) , Eric Martin (1)

1 Lab-STICC_UBS_CACS_MOCS
2 STMicroelectronics

This paper presents a methodology to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall performance of the system is significantly affected by communication architectures, as a consequence the designers need specifically optimized adapters. By explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named Space-Time AdapteR (STAR). Our design flow inputs a C description of Input/Output data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a Resource Constraints Graph (RCG). Design space exploration is then performed through associated tools, to synthesize a STAR component under time-to-market constraints. The proposed approach has been tested to design an industrial data mixing block example: an Ultra-Wideband interleaver.

Domaines: Micro et nanotechnologies/Microélectronique; Traitement du signal et de l'image [eess.SP]; Architectures Matérielles [cs.AR]; Systèmes embarqués; Théorie de l'information [cs.IT]; Théorie de l'information et codage [math.IT]; Traitement du signal et de l'image [eess.SP]

Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin. Application of a design space exploration tool to enhance interleaver generation. European Signal Processing Conference (EUSIPCO-2007), Sep 2007, Poznan, Poland. pp.XX-YY. ⟨hal-00154025⟩