Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI

Gwenolé Corre (1) , Philippe Coussy (2) , Pierre Bomel (2) , Eric Senn (2) , Eric Martin (2)

1 LESTER - Laboratoire d'Electronique des Systèmes TEmps Réel
2 Lab-STICC_UBS_CACS_MOCS

The design of complex Digital Signal Processing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory accesses constraints for the integration of dedicated hardware accelerator. Unfortunately, the traditional Matlab/ Simulink design flows gather not very flexible hardware blocs. In this paper, we present a methodology and a tool that permit the High-Level Synthesis of DSP applications, under both I/O timing and memory constraints. Based on formal models and a generic architecture, our tool GAUT helps the designer in finding a reasonable trade-off between the circuit's performance and its architectural complexity. The efficiency of our approach is demonstrated on the case study of a FFT algorithm.

Mots clés: TDSI; synthèse sous contraintes de mémorisation et de communication

Domaines: Architectures Matérielles [cs.AR]

Gwenolé Corre, Philippe Coussy, Pierre Bomel, Eric Senn, Eric Martin. Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI. GRETSI'05 (Colloque sur le Traitement du Signal et de l'Image), 2005, LOUVAIN LA NEUVE, Belgique. pp.779-782. ⟨hal-00077384⟩