Power Estimation of a C algorithm on a VLIW Processor

Nathalie Julien (1) , Eric Senn (1) , Johann Laurent , Eric Martin (1)

1 Lab-STICC_UBS_CACS_MOCS

A complete methodology to estimate power consumption directly at the C-level for on-the-shelf processors is proposed. It relies on a power model of the processor that describes the consumption variations relatively to algorithmic and configuration parameters. The algorithmic parameters represent the power and quality metrics of the code and can be predicted directly from the C-algorithm with simple assumptions on the compilation. To check the algorithm performances with the application constraints without compiling, direct estimation results on the C code can be summarized on a consumption map. This method strongly reduces the design complexity in terms of number of lines to be studied and allows to spot the 'hot parts' of the code in order to target the writing effort. Applied to a VLIW processor, the TI TMSC6201, the estimation method provides an accurate power consumption estimation together with the maximum and minimum bounds; a maximum error of 8% against measurements for only 1.3% of the code studied is obtained for a MPEG decoder; other classical DSP applications are also presented.

Mots clés: FLPA; DSP VLIW; Power consumption; Energy; Estimation

Domaines: Architectures Matérielles [cs.AR]

Nathalie Julien, Eric Senn, Johann Laurent, Eric Martin. Power Estimation of a C algorithm on a VLIW Processor. 2002, pp 100. ⟨hal-00077336⟩