High-level synthesis under I/O Timing and Memory constraints

Philippe Coussy (1) , Gwenolé Corre (2) , Pierre Bomel (1) , Eric Senn (1) , Eric Martin (1)

1 Lab-STICC_UBS_CACS_MOCS
2 LESTER - Laboratoire d'Electronique des Systèmes TEmps Réel

The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper, we present a methodology and a tool that allow the High-Level Synthesis of DSP algorithm, under both I/O timing and memory constraints. Based on formal models and a generic architecture, this tool helps the designer to find a reasonable trade-off between both the required I/O timing behavior and the internal memory access parallelism of the circuit. The interest of our approach is demonstrated on the case study of a FFT algorithm.

Mots clés: I/O and memory constraint; high level synthesis

Domaines: Architectures Matérielles [cs.AR]; Micro et nanotechnologies/Microélectronique

Philippe Coussy, Gwenolé Corre, Pierre Bomel, Eric Senn, Eric Martin. High-level synthesis under I/O Timing and Memory constraints. 2005, pp.680-683. ⟨hal-00077297⟩