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| HAL : hal-00015085, version 1 |
| DOI : 10.1109/DFTVS.1996.572037 |
| Fiche détaillée |  Récupérer au format |
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| Proceedings.-1996-IEEE-International-Symposium-on-Defect-and-Fault-Tolerance-in-VLSI-Systems-Cat.-No.96TB100081, Boston, MA : États-Unis (1996) |
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| ROM-based synthesis of fault-tolerant controllers |
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| X. Wending 1R. Rochet 1 |
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| (1996) |
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| Fault tolerance has become a major concern in the design of VLSI systems. It is especially needed in finite state machines (FSMs) where a failure can have huge consequences on the whole circuit behavior. Several methods have been proposed in the last few years to implement such features in FSMs synthesized on standard cells. At the same time, considering circuit cost, performances and design efficiency, it has been shown that large controllers should rather be synthesized on a particular ROM-based architecture. The work presented here has consisted in studying, implementing and evaluating fault tolerance methods in FSMs in a ROM-based synthesis flow. |
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| 1 : | CSI, INPG, Grenoble (CSI) |
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Institut National Polytechnique de Grenoble (INPG) |
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| 2 : | Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) |
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CNRS : UMR5159 – Université Joseph Fourier - Grenoble I – Institut National Polytechnique de Grenoble (INPG) |
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| Domaine | : | Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique |
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| ROM-based-synthesis – fault-tolerant-controllers – VLSI-systems – finite-state-machines – circuit-behavior – standard-cells – design-efficiency – synthesis-flow – IC-design |
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| hal-00015085, version 1 | |
| http://hal.archives-ouvertes.fr/hal-00015085 | |
| oai:hal.archives-ouvertes.fr:hal-00015085 | |
| Contributeur : Lucie Torella | |
| Soumis le : Vendredi 2 Décembre 2005, 14:57:51 | |
| Dernière modification le : Jeudi 23 Février 2006, 11:24:29 | |
