A VLSI implementation of parallel fast Fourier transform

A. Vacher (1) , M. Benkhebbab (1) , A. Guyot (1) , T. Rousseau (1) , A. Skaf (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés

This paper presents the design of a VLSI circuit to perform the Fourier transform using on-line most-significant-digit-first arithmetic. First, the principles of the pipelined fast Fourier transform are recalled, and a folded pipeline is introduced. Then on-line operators and operator merging rules are used to design a cost effective butterfly operator. Finally a circuit with 8 butterflies is described and compared to other realizations.

Mots clés: VLSI-implementation; parallel-fast-Fourier-transform; VLSI-circuit-design; on-line-most-significant-digit-first-arithmetic; pipelined-fast-Fourier-transform; folded-pipeline; on-line-operators; operator-merging-rules; cost-effective-butterfly-operator

Domaines: Micro et nanotechnologies/Microélectronique

A. Vacher, M. Benkhebbab, A. Guyot, T. Rousseau, A. Skaf. A VLSI implementation of parallel fast Fourier transform. Proceedings.-The-European-Design-and-Test-Conference.-EDAC,-The-European-Conference-on-Design-Automation.-ETC-European-Test-Conference.-EUROASIC,-The-European-Event-in-ASIC-Design-Cat.-No.94TH0634-6., 1994, Paris, France. pp.250-5, ⟨10.1109/EDTC.1994.326869⟩. ⟨hal-00014947⟩