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| HAL : hal-00014947, version 1 |
| DOI : 10.1109/EDTC.1994.326869 |
| Fiche détaillée |  Récupérer au format |
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| Proceedings.-The-European-Design-and-Test-Conference.-EDAC,-The-European-Conference-on-Design-Automation.-ETC-European-Test-Conference.-EUROASIC,-The-European-Event-in-ASIC-Design-Cat.-No.94TH0634-6., Paris : France (1994) |
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| A VLSI implementation of parallel fast Fourier transform |
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| A. VACHER 1M. Benkhebbab 1 |
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| (1994) |
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| This paper presents the design of a VLSI circuit to perform the Fourier transform using on-line most-significant-digit-first arithmetic. First, the principles of the pipelined fast Fourier transform are recalled, and a folded pipeline is introduced. Then on-line operators and operator merging rules are used to design a cost effective butterfly operator. Finally a circuit with 8 butterflies is described and compared to other realizations. |
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| 1 : | Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) |
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CNRS : UMR5159 – Université Joseph Fourier - Grenoble I – Institut National Polytechnique de Grenoble (INPG) |
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| Domaine | : | Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique |
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| VLSI-implementation – parallel-fast-Fourier-transform – VLSI-circuit-design – on-line-most-significant-digit-first-arithmetic – pipelined-fast-Fourier-transform – folded-pipeline – on-line-operators – operator-merging-rules – cost-effective-butterfly-operator |
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| hal-00014947, version 1 | |
| http://hal.archives-ouvertes.fr/hal-00014947 | |
| oai:hal.archives-ouvertes.fr:hal-00014947 | |
| Contributeur : Lucie Torella | |
| Soumis le : Mercredi 30 Novembre 2005, 15:26:17 | |
| Dernière modification le : Jeudi 23 Février 2006, 12:39:28 | |
