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| HAL : hal-00014927, version 1 |
| Fiche détaillée |  Récupérer au format |
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| ESSCIRC-'95.-Twenty-First-European-Solid-State-Circuits-Conference.-Proceedings., Lille : France (1995) |
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| DCFL- and DPTL-based approaches to self-timed GaAs circuits |
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| R.P. Ribas 1A. Guyot 2 |
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| (1995) |
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| This paper presents two GaAs MESFET-based methodologies to design self-timed circuits. The first approach uses direct-coupled FET logic (DCFL) to implement Boolean equations in sum-of-sums form, resulting in a simple and fast way to design hazard-free functional blocks in asynchronous systems. The second approach deals with an adaptation of the ratioless differential pass-transistor logic (DPTL) technique to construct such functional blocks. This approach is demonstrated to be very effective in minimizing area overhead and power consumption. The methodologies are described and validated through a radix-2 redundant divider implementation. |
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| 1 : | Univ. Federal do Rio Grande do Sul |
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Univ. Federal do Rio Grande do Sul |
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| 2 : | Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) |
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CNRS : UMR5159 – Université Joseph Fourier - Grenoble I – Institut National Polytechnique de Grenoble (INPG) |
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| Domaine | : | Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique |
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| self-timed-GaAs-circuits – GaAs-MESFET – direct-coupled-FET-logic – Boolean-equations – asynchronous-systems – ratioless-differential-pass-transistor-logic – power-consumption – radix-2-redundant-divider-implementation – VLSI- – GaAs- |
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| hal-00014927, version 1 | |
| http://hal.archives-ouvertes.fr/hal-00014927 | |
| oai:hal.archives-ouvertes.fr:hal-00014927 | |
| Contributeur : Lucie Torella | |
| Soumis le : Mercredi 30 Novembre 2005, 13:58:32 | |
| Dernière modification le : Jeudi 23 Février 2006, 11:51:16 | |
