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| HAL : hal-00013902, version 1 |
| Fiche détaillée |  Récupérer au format |
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| Russian Microelectronics May-June ; 24(3) (1995) 186-90 |
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| Design of self-testing RAMs |
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| V.-N. Yarmolik 1G.-R. Memetov 1 |
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| (1995) |
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| RAMs built in complex VLSIs are frequently used at present. Self-testing is the most appropriate testing method for these devices. RAM testing should be as complete as possible because RAM is one of the major parts in any computer system. In this work we propose a self-testing RAM design that allows detection of all faults of given types. As a result, a self-testing RAM with 100-% detectability of certain faults was designed. |
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| 1 : | Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) |
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CNRS : UMR5159 – Université Joseph Fourier - Grenoble I – Institut National Polytechnique de Grenoble (INPG) |
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| 2 : | iROc Technologies (IROC TECHNOLOGIES) |
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Cadence Connection – EDA Consortium – FSA – Cubic Micro |
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| Domaine | : | Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique |
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| self-testing-RAMs – complex-VLSI – testing-method – fault-detection – detectability- – memory-testing – linear-compression – testing-algorithms |
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| hal-00013902, version 1 | |
| http://hal.archives-ouvertes.fr/hal-00013902 | |
| oai:hal.archives-ouvertes.fr:hal-00013902 | |
| Contributeur : Lucie Torella | |
| Soumis le : Mardi 15 Novembre 2005, 12:31:28 | |
| Dernière modification le : Lundi 10 Avril 2006, 15:20:34 | |
