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| HAL : hal-00013449, version 1 |
| Fiche détaillée |  Récupérer au format |
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| FTCS-Digest-of-Papers.-16th-Annual-International-Symposium-on-Fault-Tolerant-Computing-Systems-Cat.-No.86CH2335-8, Vienne : Autriche (1986) |
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| Design of NMOS strongly fault secure circuits using unidirectional errors detecting codes |
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| M. Nicolaidis 1, 2B. Courtois 1 |
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| (1986) |
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| The necessity to consider fault models representing real faults occurring in integrated circuits led recently to the definitions of low-level fault hypotheses such as transistors stuck-on, stuck-open, and cuts of metallization. It is then natural to base the design of self-checking systems on this type of fault hypotheses. General layout rules are derived for the design of strongly fault secure (SFS) NMOS circuits (i.e. for the largest class of circuits that achieve the totally self-checking goal). Those rules are derived in order to detect unidirectional errors, which have been recognized as a large category of errors appearing in integrated circuits. Examples of the application of these layout rules are given for the design of PLAs, ROMs, and ALUs. |
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| 1 : | Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) |
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CNRS : UMR5159 – Université Joseph Fourier - Grenoble I – Institut National Polytechnique de Grenoble (INPG) |
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| 2 : | iROc Technologies (IROC TECHNOLOGIES) |
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Cadence Connection – EDA Consortium – FSA – Cubic Micro |
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| Domaine | : | Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique |
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| NMOS- – fault-secure-circuits – unidirectional-errors-detecting-codes – fault-models – integrated-circuits – fault-hypotheses |
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| hal-00013449, version 1 | |
| http://hal.archives-ouvertes.fr/hal-00013449 | |
| oai:hal.archives-ouvertes.fr:hal-00013449 | |
| Contributeur : Lucie Torella | |
| Soumis le : Mardi 8 Novembre 2005, 14:41:54 | |
| Dernière modification le : Jeudi 23 Mars 2006, 15:30:10 | |
