Towards automatic failure analysis of complex ICs through e-beam testing
Résumé
A strategy is derived for failure analysis in random logic devices such as microprocessors and other VLSI chips when the electrical scheme is not known. This strategy is based on the use of a test tool composed of a scanning electron microscope allied to voltage contrast, and exerciser, an image processing system, and a control and data processing system. The tool is described, and first results of the application of the method, based on image comparison, are shown. Directions for future research are mentioned.