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| HAL : hal-00008389, version 1 |
| Fiche détaillée |  Récupérer au format |
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| FR2721135 (1995-12-15) - France |
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| Correction d'erreurs dans une mémoire |
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| M. Nicolaidis 1, 2F.L. Vargas |
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| (15/12/1995) |
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| Static memory comprising memory cells (MC) arranged in rows and columns, each row of cells constituting of at least one word and a corresponding error control code. Each cell column comprises at least one specific power line (Vcc', GND') connected to a general power line (Vcc', GND') of the memory through a current detector (10, 12). Each detector activates an error signal if the associated specific supply line current exceeds a predetermined threshhold. |
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| 1 : | Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) |
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CNRS : UMR5159 – Université Joseph Fourier - Grenoble I – Institut National Polytechnique de Grenoble (INPG) |
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| 2 : | iROc Technologies (IROC TECHNOLOGIES) |
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Cadence Connection – EDA Consortium – FSA – Cubic Micro |
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| Domaine | : | Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique |
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| CIB Intern.: G06F11/00 – G11C29/50 – G06F11/10 – G06F11/00 – G11C29/04 – (IPC1-7): G11C29/00 – G11C7/02 CIB Europ.: G06F11/00B3 |
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| hal-00008389, version 1 | |
| http://hal.archives-ouvertes.fr/hal-00008389 | |
| oai:hal.archives-ouvertes.fr:hal-00008389 | |
| Contributeur : Lucie Torella | |
| Soumis le : Vendredi 2 Septembre 2005, 17:28:28 | |
| Dernière modification le : Vendredi 10 Février 2006, 07:11:10 | |
