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| HAL : hal-00008388, version 1 |
| Fiche détaillée |  Récupérer au format |
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| US5640341 (07/06/1997) - France |
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| Memory cell insensitive to collisions of heavy ions |
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| D. Bessot 1R. Velazco 1 |
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| (07/06/1997) |
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| PCT No. PCT/FR94/00287 Sec. 371 Date Dec. 11, 1995 Sec. 102(e) Date Dec. 11, 1995 PCT Filed Mar. 16, 1994 PCT Pub. No. WO94/2214 PCT Pub. Date Sep. 29, 1994A differential memory cell comprises two sets, each including first P-channel, second N-channel and third N-channel transistors, connected in series between a high and a low supply voltage. The gate of one of the N-channel transistors of each set is connected to the output node of the other set. The gate of the other N-channel transistor of each set is connected to the gate of the first transistor of the same set. A fourth P-channel transistor, associated with each set, is connected between the high voltage and the gate of the first transistor of the set. A fifth P-channel transistor, associated with each set, is connected between the gate of the first transistor of the set and a read/write line or the low voltage. |
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| 1 : | Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) |
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CNRS : UMR5159 – Université Joseph Fourier - Grenoble I – Institut National Polytechnique de Grenoble (INPG) |
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| Domaine | : | Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique |
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| CIB Intern.: G11C11/412 – G11C11/412 – (IPC1-7): G11C11/412 CIB Europ.: G11C11/412R |
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| hal-00008388, version 1 | |
| http://hal.archives-ouvertes.fr/hal-00008388 | |
| oai:hal.archives-ouvertes.fr:hal-00008388 | |
| Contributeur : Lucie Torella | |
| Soumis le : Vendredi 2 Septembre 2005, 16:42:10 | |
| Dernière modification le : Vendredi 10 Février 2006, 08:08:11 | |
